| Logic Function |
Multiplexer |
| Configuration |
1 x 8:1 |
| Number of Elements per Chip |
1 |
| Number of Inputs per Chip |
8 |
| Number of Outputs per Chip |
1 |
| Number of Input Enables per Element |
0 |
| Number of Output Enables per Element |
1 |
| Number of Selection Inputs per Element |
3 |
| Input Signal Type |
Single-Ended |
| Output Signal Type |
Differential |
| Output Type |
3-State |
| Parity Invert Input |
No |
| Polarity |
Inverting/Non-Inverting |
| Logic Family |
ACT |
| Process Technology |
CMOS |
| Minimum Operating Supply Voltage (V) |
4.5 |
| Maximum Operating Supply Voltage (V) |
5.5 |
| Typical Operating Supply Voltage (V) |
5 |
| Power Supply Type |
Single |
| Minimum Operating Temperature (°C) |
-40 |
| Maximum Operating Temperature (°C) |
85 |
| Maximum Propagation Delay Time @ Maximum CL (ns) |
12.5@5V |
| Absolute Propagation Delay Time (ns) |
18.5 |
| Propagation Delay Test Condition (pF) |
50 |
| Maximum High Level Output Current (mA) |
-24 |
| Maximum Low Level Output Current (mA) |
24 |
| Maximum Quiescent Current (uA) |
4 |
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