| Type |
D-Type |
| Latch Mode |
Transparent |
| Bus Hold |
Yes |
| Logic Family |
ALVC |
| Process Technology |
CMOS |
| Number of Elements per Chip |
2 |
| Number of Channels per Chip |
16 |
| Number of Inputs per Chip |
16 |
| Number of Outputs per Chip |
16 |
| Number of Output Enables per Element |
1 |
| Number of Input Enables per Element |
1 |
| Number of Selection Inputs per Element |
0 |
| Output Type |
3-State |
| Polarity |
Non-Inverting |
| Set/Reset |
No |
| Minimum Operating Supply Voltage (V) |
1.65 |
| Maximum Operating Supply Voltage (V) |
3.6 |
| Typical Operating Supply Voltage (V) |
1.8|2.5|3.3 |
| Minimum Operating Temperature (°C) |
-40 |
| Maximum Operating Temperature (°C) |
85 |
| Supplier Temperature Grade |
Commercial |
| Maximum Propagation Delay Time @ Maximum CL (ns) |
4.3@2.7V|3.6@3.3V |
| Absolute Propagation Delay Time (ns) |
4.9 |
| Propagation Delay Test Condition (pF) |
50 |
| Maximum High Level Output Current (mA) |
-24 |
| Maximum Low Level Output Current (mA) |
24 |
| Maximum Quiescent Current (uA) |
40 |