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▪ 4–12 Low-power HCSL (LP-HCSL) outputs
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▪ Integrated terminations eliminate up to 4 resistors per output pair
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▪ Dedicated OE# pins support PCIe CLKREQ# function
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▪ Up to 9 selectable SMBus addresses (9ZXL12)
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▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topologies
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| CATALOG |
9ZXL0451EKILFT COUNTRY OF ORIGIN
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9ZXL0451EKILFT PARAMETRIC INFO
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9ZXL0451EKILFT PACKAGE INFO
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9ZXL0451EKILFT MANUFACTURING INFO
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9ZXL0451EKILFT PACKAGING INFO
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9ZXL0451EKILFT APPLICATIONS
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COUNTRY OF ORIGIN
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China
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Thailand
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Taiwan (Province of China)
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Malaysia
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PARAMETRIC INFO
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| Number of Outputs per Chip |
4 |
| Clock Input Frequency (MHz) |
98.5 to 102.5 |
| Typical Duty Cycle (%) |
50.3 |
| Output Logic Level |
HCSL |
| Minimum Operating Temperature (°C) |
-40 |
| Maximum Operating Temperature (°C) |
85 |
| Supplier Temperature Grade |
Industrial |
| Minimum Operating Supply Voltage (V) |
3.135 |
| Typical Operating Supply Voltage (V) |
3.3 |
| Maximum Operating Supply Voltage (V) |
3.465 |
| Number of Clock Inputs |
1 |
| Spread Spectrum |
Yes |
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PACKAGE INFO
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| Supplier Package |
VFQFPN EP |
| Basic Package Type |
Non-Lead-Frame SMT |
| Pin Count |
32 |
| Lead Shape |
No Lead |
| PCB |
32 |
| Tab |
N/R |
| Package Length (mm) |
5 |
| Package Width (mm) |
5 |
| Package Height (mm) |
0.85(Max) |
| Package Diameter (mm) |
N/R |
| Mounting |
Surface Mount |
| Package Material |
Plastic |
| Package Family Name |
QFP |
| Package Outline |
Link to Datasheet |
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MANUFACTURING INFO
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| MSL |
3 |
| Lead Finish(Plating) |
Matte Sn annealed |
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PACKAGING INFO
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| Packaging Suffix |
T |
| Packaging |
Tape and Reel |
| Packaging Document |
Link to Datasheet |
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APPLICATIONS
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| ▪ Servers/High-performance Computing |
| ▪ nVME Storage |
| ▪ Networking |
| ▪ Accelerators |
| ▪ Industrial Control |
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