|
|
• Input voltage range: 4.5 V to 16 V
|
• Maximum output current: 800 mA
|
• Noise spectral density: 1.7 nV√Hz typical from 10 kHz to 1 MHz
|
• Dropout voltage: 0.6 V at VOUT = 5 V, 800 mA load
|
|
| CATALOG |
ADM7150ACPZ-3.3-R7 COUNTRY OF ORIGIN
|
ADM7150ACPZ-3.3-R7 PARAMETRIC INFO
|
ADM7150ACPZ-3.3-R7 PACKAGE INFO
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ADM7150ACPZ-3.3-R7 MANUFACTURING INFO
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ADM7150ACPZ-3.3-R7 PACKAGING INFO
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ADM7150ACPZ-3.3-R7 ECAD MODELS
|
ADM7150ACPZ-3.3-R7 APPLICATIONS
|
|
COUNTRY OF ORIGIN
|
Korea (Republic of)
|
|
PARAMETRIC INFO
|
| Type |
LDO |
| Number of Outputs |
1 |
| Maximum Output Current (A) |
0.8 |
| Minimum Operating Temperature (°C) |
-40 |
| Maximum Operating Temperature (°C) |
125 |
| Output Type |
Fixed |
| Output Voltage Range (V) |
1.8 to 10 |
| Regulation Condition Change In Load |
799mA |
| Junction to Ambient |
36.7°C/W |
| Junction to Case |
23.5°C/W |
| Polarity |
Positive |
| Special Features |
Current Limit|Thermal Protection |
| Load Regulation |
0.4%/A(Typ) |
| Line Regulation |
0.01%/V |
| Maximum Dropout Voltage @ Current (V) |
0.5@400mA|1@800mA |
| Minimum Input Voltage (V) |
4.5 |
| Maximum Input Voltage (V) |
16 |
| Output Voltage (V) |
3.3 |
| Typical Quiescent Current (mA) |
4.3 |
| Typical Dropout Voltage @ Current (V) |
0.3@400mA|0.6@800mA |
| Accuracy (%) |
±1 |
| Minimum Storage Temperature (°C) |
-65 |
| Maximum Storage Temperature (°C) |
150 |
| Noise Spectral Density (uV/rtHz) |
0.0017@1000kHz |
| Typical PSRR (dB) |
95 |
| Typical Output Capacitance (uF) |
10 |
| Typical Output Noise Voltage (uVrms) |
1.6 |
| Pass Element Type |
PMOS |
| Output Capacitor Type |
Ceramic |
|
|
PACKAGE INFO
|
| Supplier Package |
LFCSP EP |
| Basic Package Type |
Non-Lead-Frame SMT |
| Pin Count |
8 |
| Lead Shape |
No Lead |
| PCB |
8 |
| Tab |
N/R |
| Pin Pitch (mm) |
0.5 |
| Package Length (mm) |
3 |
| Package Width (mm) |
3 |
| Package Height (mm) |
0.73 |
| Package Diameter (mm) |
N/R |
| Package Overall Length (mm) |
3 |
| Package Overall Width (mm) |
3 |
| Package Overall Height (mm) |
0.75 |
| Seated Plane Height (mm) |
0.75 |
| Mounting |
Surface Mount |
| Terminal Width (mm) |
0.25 |
| Package Weight (g) |
N/A |
| Package Material |
Plastic |
| Package Description |
Lead Frame Chip Scale Package, Exposed Pad |
| Package Family Name |
CSP |
| Jedec |
MO-229WEED |
| Package Outline |
Link to Datasheet |
|
|
MANUFACTURING INFO
|
| MSL |
3 |
| Maximum Reflow Temperature (°C) |
260 |
| Reflow Solder Time (Sec) |
30 |
| Number of Reflow Cycle |
3 |
| Standard |
J-STD-020D |
| Maximum Wave Temperature (°C) |
N/R |
| Wave Solder Time (Sec) |
N/R |
| Lead Finish(Plating) |
Matte Sn annealed |
| Under Plating Material |
Ag |
| Terminal Base Material |
Cu Alloy |
| Number of Wave Cycles |
N/R |
|
|
PACKAGING INFO
|
| Packaging Suffix |
R7 |
| Packaging |
Tape and Reel |
| Quantity Of Packaging |
1500 |
| Reel Diameter (in) |
7 |
| Tape Pitch (mm) |
8 |
| Tape Width (mm) |
12 |
| Component Orientation |
Q2 |
| Packaging Document |
Link to Datasheet |
| Tape Material |
Plastic |
| Tape Type |
Embossed |
|
| |
| ECAD MODELS |
 |
|
| APPLICATIONS |
| • Regulated power noise sensitive applications RF mixers, phase-locked loops (PLLs), voltage-controlled oscillators (VCOs), and PLLs with integrated VCOs |
| • Communications and infrastructure |
| • Cable digital-to-analog converter (DAC) drivers |
| • Backhaul and microwave links |
| |
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