EP2C5T144C8N Intel / Altera IC FPGA 89 I/O 144TQFP

label:

2023/10/12 411

■ High-density architecture with 4,608 to 68,416 LEs
● M4K embedded memory blocks
● Up to 1.1 Mbits of RAM available without reducing available logic
● 4,096 memory bits per block (4,608 bits per block including 512 parity bits)
● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
● True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes
● Byte enables for data input masking during writes
● Up to 260-MHz operation

■ Embedded multipliers
● Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance
● Optional input and output registers

■ Advanced I/O support
● High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL
● Single-ended I/O standard support, including 2.5-V and 1.8-V, SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL
● Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces
● PCI Express with an external TI PHY and an Altera PCI Express ×1 Megacore® function
● 133-MHz PCI-X 1.0 specification compatibility
● High-speed external memory support, including DDR, DDR2, and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use
● Three dedicated registers per I/O element (IOE): one input register, one output register, and one output-enable register
● Programmable bus-hold feature
● Programmable output drive strength feature
● Programmable delays from the pin to the IOE or logic array
● I/O bank grouping for unique VCCIO and/or VREF bank settings
● MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and 3.3-interfaces
● Hot-socketing operation support
● Tri-state with weak pull-up on I/O pins before and during configuration
● Programmable open-drain outputs
● Series on-chip termination support

■ Flexible clock management circuitry
● Hierarchical clock network for up to 402.5-MHz performance
● Up to four PLLs per device provide clock multiplication and division, phase shifting, programmable duty cycle, and external clock outputs, allowing system-level clock management and skew control
● Up to 16 global clock lines in the global clock network that drive throughout the entire device

■ Device configuration
● Fast serial configuration allows configuration times less than 100 ms
● Decompression feature allows for smaller programming file storage and faster configuration times
● Supports multiple configuration modes: active serial, passive serial, and JTAG-based configuration
● Supports configuration through low-cost serial configuration devices
● Device configuration supports multiple voltages (either 3.3, 2.5, or 1.8 V)

■ Intellectual property
● Altera megafunction and Altera MegaCore function support, and Altera Megafunctions Partners Program (AMPPSM) megafunction support, for a wide range of embedded processors, on-chip and off-chip interfaces, peripheral functions, DSP functions, and communications functions and protocols. Visit the Altera IPMegaStore at www.altera.com to download IP MegaCore functions.
● Nios II Embedded Processor support

CATALOG

EP2C5T144C8N COUNTRY OF ORIGIN

EP2C5T144C8N PARAMETRIC INFO

EP2C5T144C8N PACKAGE INFO

EP2C5T144C8N MANUFACTURING INFO

EP2C5T144C8N PACKAGING INFO

EP2C5T144C8N ECAD MODELS

EP2C5T144C8N FYNCTONAL BLOCK DIAGRAM

EP2C5T144C8N APPLICATIONS

COUNTRY OF ORIGIN

Malaysia

PARAMETRIC INFO

Device Logic Units	4608
Device Logic Cells	4608
Maximum Number of User I/Os	89
Number of I/O Banks	4
Device Number of DLLs/PLLs	2
Number of Multipliers	13 (18x18)
Maximum DSP Block Frequency (MHz)	180.57
Maximum LVDS Data Rate (Mbps)	311
Tradename	Cyclone
Maximum I/O Performance	640Mbps
RAM Bits (Kbit)	117
Total Number of Block RAM	26
Program Memory Type	SRAM
Family Name	Cyclone® II
Process Technology	90nm
Speed Grade	8
Differential I/O Standards Supported	LVDS\|PCI-X
Single-Ended I/O Standards Supported	LVDS\|PCI-X
JTAG Support (-)	Yes
Maximum Supply Current (mA)	10(Typ)
External Memory Interface	DDR SDRAM\|QDR II+SRAM
Copy Protection	No
Supported IP Core	Viterbi Compiler, Low-Speed/Hybrid Serial Decoder\|V1 ColdFire\|SpeedView Enabled JPEG Encoder (SVE-JPEG-E)\|10 Gigabit Ethernet MAC\| 32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz
Shift Registers	Utilize Memory
Programmability	No
Supported IP Core Manufacture	Altera/Freescale/CAST, Inc/MorethanIP/PLDA
In-System Programmability	Yes
Number of Look-up Table Input	4
Reprogrammability Support	No
Maximum Internal Frequency (MHz)	402.58
Number of Global Clocks	8
Maximum Operating Supply Voltage (V)	1.25
I/O Voltage (V)	1.5\|1.8\|2.5\|3.3
Minimum Operating Temperature (°C)	0
Maximum Operating Temperature (°C)	85
Temperature Flag	Jun
Supplier Temperature Grade	Commercial
Digital Control Impedance	No
Minimum Operating Supply Voltage (V)	1.15
Typical Operating Supply Voltage (V)	1.2
Tolerant Configuration Interface Voltage (V)	1.5\|1.8\|2.5\|3.3
Maximum Storage Temperature (°C)	150
Minimum Storage Temperature (°C)	-65

PACKAGE INFO

Supplier Package	TQFP
Basic Package Type	Lead-Frame SMT
Pin Count	144
Lead Shape	Gull-wing
PCB	144
Tab	N/R
Pin Pitch (mm)	0.5
Package Length (mm)	20
Package Width (mm)	20
Package Height (mm)	1.4
Package Diameter (mm)	N/R
Package Overall Length (mm)	22
Package Overall Width (mm)	22
Package Overall Height (mm)	1.6(Max)
Seated Plane Height (mm)	1.6(Max)
Mounting	Surface Mount
Package Weight (g)	1.1
Package Material	Plastic
Package Description	Thin Quad Flat Package
Package Family Name	QFP
Jedec	MS-026BFB
Package Outline	Link to Datasheet

MANUFACTURING INFO

MSL	3
Maximum Reflow Temperature (°C)	260
Reflow Solder Time (Sec)	30
Number of Reflow Cycle	3
Standard	IPC-1752
Reflow Temp. Source	Link to Datasheet
Maximum Wave Temperature (°C)	N/R
Wave Solder Time (Sec)	N/R
Wave Temp. Source	Link to Datasheet
Lead Finish(Plating)	Matte Sn annealed
Under Plating Material	N/A
Terminal Base Material	Cu Alloy
Number of Wave Cycles	N/R

PACKAGING INFO

Packaging	Tray
Quantity Of Packaging	60
Packaging Document	Link to Datasheet

ECAD MODELS

FYNCTONAL BLOCK DIAGRAM

APPLICATIONS

■ Up to 150 18 × 18 multipliers

■ Up to 1.1 Mbit of on-chip embedded memory

■ High-speed interfaces to external memory

■ DSP intellectual property (IP) cores

■ DSP Builder interface to The Mathworks Simulink and Matlab design environment

■ DSP Development Kit, Cyclone II Edition