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• Ultra Low SSB Phase Noise Floor:-153 dBc/Hz @ 10 kHz offset @ 100 MHz Reference Frequency.
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• Programmable Divider (N= 12 - 259) Operating up to 7 GHz
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• Open Collector Output Buffer Amplifiers for Interfacing w/ Op-Amp Based Loop Filter
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• Reversible Polarity PFD w/ Lock Detect Output
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• 32 Lead 5x5mm SMT Package: 25mm2
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CATALOG |
HMC698LP5ETR COUNTRY OF ORIGIN
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HMC698LP5ETR PARAMETRIC INFO
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HMC698LP5ETR PACKAGE INFO
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HMC698LP5ETR MANUFACTURING INFO
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HMC698LP5ETR PACKAGING INFO
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HMC698LP5ETR ECAD MODELS
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HMC698LP5ETR FUNCTIONAL DIAGRAM
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HMC698LP5ETR APPLICATIONS
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COUNTRY OF ORIGIN
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Malaysia
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PARAMETRIC INFO
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Number of Outputs per Chip |
1 |
Clock Input Frequency (MHz) |
10 to 1300 |
Input Logic Level |
CMOS|TTL |
Minimum Operating Temperature (°C) |
-40 |
Maximum Operating Temperature (°C) |
85 |
Input Signal Type |
Differential |
Output Signal Type |
Single-Ended |
Hitless Protection Switching |
No |
Frequency Margining |
No |
Programmability |
Yes |
Minimum Storage Temperature (°C) |
-65 |
Maximum Storage Temperature (°C) |
150 |
Minimum Operating Supply Voltage (V) |
4.75 |
Typical Operating Supply Voltage (V) |
5 |
Maximum Operating Supply Voltage (V) |
5.25 |
Number of Clock Inputs |
1 |
Spread Spectrum |
No |
Maximum Supply Current (mA) |
340 |
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PACKAGE INFO
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Supplier Package |
LFCSP EP |
Basic Package Type |
Non-Lead-Frame SMT |
Pin Count |
32 |
Lead Shape |
No Lead |
PCB |
32 |
Tab |
N/R |
Pin Pitch (mm) |
0.5 |
Package Length (mm) |
5 |
Package Width (mm) |
5 |
Package Height (mm) |
0.88 |
Package Diameter (mm) |
N/R |
Package Overall Length (mm) |
5 |
Package Overall Width (mm) |
5 |
Package Overall Height (mm) |
0.9 |
Seated Plane Height (mm) |
0.9 |
Mounting |
Surface Mount |
Package Weight (g) |
N/A |
Package Material |
Plastic |
Package Description |
Lead Frame Chip Scale Package, Exposed Pad |
Package Family Name |
CSP |
Jedec |
MO-220VHHD-4 |
Package Outline |
Link to Datasheet |
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MANUFACTURING INFO
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MSL |
1 |
Maximum Reflow Temperature (°C) |
260 |
Reflow Solder Time (Sec) |
30 |
Number of Reflow Cycle |
3 |
Standard |
J-STD-020D |
Maximum Wave Temperature (°C) |
N/R |
Wave Solder Time (Sec) |
N/R |
Lead Finish(Plating) |
Matte Sn annealed |
Number of Wave Cycles |
N/R |
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PACKAGING INFO
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Packaging Suffix |
TR |
Packaging |
Tape and Reel |
Quantity Of Packaging |
500 |
Reel Diameter (in) |
13 |
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ECAD MODELS |

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FUNCTIONAL DIAGRAM
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APPLICATIONS
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• Satellite Communication Systems
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• Point-to-Point Radios
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• Military Applications
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• Sonet Clock Generation
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