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• Output Current: 5A
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• Dropout Voltage: 85mV Typical
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• Digitally Programmable VOUT: 0.8V to 1.8V
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• Digital Output Margining: ±1%, ±3% or ±5%
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• Low Output Noise: 25µVRMS (10Hz to 100kHz)
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• Parallel Multiple Devices for 10A or More
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• Precision Current Limit: ±20%
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• ±1% Accuracy Over Line, Load and Temperature
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• Stable with Low ESR Ceramic Output Capacitors(15µF Minimum)
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• High Frequency PSRR: 30dB at 1MHz
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• Enable Function Turns Output On/Off
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• VIOC Pin Controls Buck Converter to Maintain LowPower Dissipation and Optimize Efficiency
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• PWRGD/UVLO/Thermal Shutdown Flag
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• Current Limit with Foldback Protection
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• Thermal Shutdown
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• 28-Lead (4mm × 5mm × 0.75mm) QFN Package
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| CATALOG |
LT3070EUFD#PBF Country of Origin
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LT3070EUFD#PBF Parametric Info
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LT3070EUFD#PBF Package Info
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LT3070EUFD#PBF Manufacturing Info
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LT3070EUFD#PBF Packaging Info
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LT3070EUFD#PBF ECAD Models
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LT3070EUFD#PBF functional BLOCK DIAGRAM
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LT3070EUFD#PBF APPLICATIONS
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COUNTRY OF ORIGIN
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Malaysia
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PARAMETRIC INFO
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| Type |
LDO |
| Number of Outputs |
1 |
| Maximum Output Current (A) |
5 |
| Minimum Operating Temperature (°C) |
-40 |
| Maximum Operating Temperature (°C) |
125 |
| Output Type |
Selectable |
| Output Voltage Range (V) |
<1.8|1.8 to 10 |
| Regulation Condition Change In Load |
4.99A |
| Regulation Condition Change In Line |
1.65V |
| Junction to Ambient |
35°C/W |
| Polarity |
Positive |
| Special Features |
Current Limit|Reverse Current Protection|Thermal Shutdown Protection |
| Load Regulation |
-7mV |
| Line Regulation |
1mV |
| Maximum Dropout Voltage @ Current (V) |
0.035@1A|0.065@2.5A|0.12@5A |
| Minimum Input Voltage (V) |
0.95 |
| Maximum Input Voltage (V) |
3 |
| Output Voltage (V) |
0.8 to 1.8 |
| Typical Dropout Voltage @ Current (V) |
0.02@1A|0.05@2.5A|0.085@5A |
| Accuracy (%) |
±1 |
| Supplier Temperature Grade |
Extended |
| Minimum Storage Temperature (°C) |
-65 |
| Maximum Storage Temperature (°C) |
150 |
| Typical Bias Voltage (VDC) |
2.2 to 3.6 |
| Typical PSRR (dB) |
75 |
| Typical Output Capacitance (uF) |
15(Min) |
| Typical Output Noise Voltage (uVrms) |
25 |
| Pass Element Type |
NMOS |
| Output Capacitor Type |
Ceramic |
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PACKAGE INFO
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| Supplier Package |
QFN EP |
| Basic Package Type |
Non-Lead-Frame SMT |
| Pin Count |
28 |
| Lead Shape |
No Lead |
| PCB |
28 |
| Tab |
N/R |
| Pin Pitch (mm) |
0.5 |
| Package Length (mm) |
5 |
| Package Width (mm) |
4 |
| Package Height (mm) |
0.75(Max) |
| Package Diameter (mm) |
N/R |
| Package Overall Length (mm) |
5 |
| Package Overall Width (mm) |
4 |
| Package Overall Height (mm) |
0.75 |
| Seated Plane Height (mm) |
0.75 |
| Mounting |
Surface Mount |
| Package Weight (g) |
N/A |
| Package Material |
Plastic |
| Package Description |
Quad Flat No Lead Package, Exposed Pad |
| Package Family Name |
QFN |
| Jedec |
MO-220WGHD-3 |
| Package Outline |
Link to Datasheet |
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MANUFACTURING INFO
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| MSL |
1 |
| Maximum Reflow Temperature (°C) |
260 |
| Reflow Solder Time (Sec) |
30 |
| Number of Reflow Cycle |
3 |
| Standard |
J-STD-020D |
| Reflow Temp. Source |
Link to Datasheet |
| Maximum Wave Temperature (°C) |
N/R |
| Wave Solder Time (Sec) |
N/R |
| Lead Finish(Plating) |
Matte Sn annealed |
| Under Plating Material |
Ag |
| Terminal Base Material |
Cu Alloy |
| Number of Wave Cycles |
N/R |
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PACKAGING INFO
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| Packaging |
Tube |
| Quantity Of Packaging |
73 |
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ECAD MODELS
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| FUNCTIONAL BLOCK DIAGRAM |
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APPLICATIONS
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• FPGA and DSP Supplies
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• ASIC and Microprocessor Supplies
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• Servers and Storage Devices
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• Post Buck Regulation and Supply Isolation
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