| Logic Family |
ACT |
| Logic Function |
Bus Transceiver |
| Data Flow Direction |
Bi-Directional |
| Number of Direction Control Inputs |
1 Low/High |
| Number of Elements per Chip |
1 |
| Number of Channels per Chip |
8 |
| Number of Selection Inputs per Element |
0 |
| Number of Input Enables per Element |
0 |
| Number of Output Enables per Element |
1 Low |
| Output Type |
3-State |
| Polarity |
Non-Inverting |
| Input Level |
TTL |
| Output Level |
CMOS |
| Bus Hold |
No |
| Process Technology |
CMOS |
| Minimum Operating Temperature (°C) |
-40 |
| Maximum Operating Temperature (°C) |
85 |
| Supplier Temperature Grade |
Commercial |
| Minimum Operating Supply Voltage (V) |
4.5 |
| Maximum Operating Supply Voltage (V) |
5.5 |
| Typical Operating Supply Voltage (V) |
5 |
| Maximum High Level Output Current (mA) |
-24 |
| Maximum Low Level Output Current (mA) |
24 |
| Maximum Quiescent Current (uA) |
4 |
| Maximum Propagation Delay Time @ Maximum CL (ns) |
8@5V |
| Propagation Delay Test Condition (pF) |
50 |
| Absolute Propagation Delay Time (ns) |
12 |
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