SN74HC132DR Texas Instruments IC GATE NAND SCHMITT 4CH 14SOIC

label:
2024/01/17 80


• Buffered inputs
• Wide operating temperature range: –40°C to +85°C
• Supports fanout up to 10 LSTTL loads  
• Significant power reduction compared to LSTTL logic ICs


CATALOG
SN74HC132DR COUNTRY OF ORIGIN
SN74HC132DR PARAMETRIC INFO
SN74HC132DR PACKAGE INFO
SN74HC132DR MANUFACTURING INFO  
SN74HC132DR PACKAGING INFO
SN74HC132DR ECAD MODELS
SN74HC132DR FUNCTIONAL BLOCK DIAGRAM  
SN74HC132DR APPLICATIONS


COUNTRY OF ORIGIN
Malaysia
Taiwan (Province of China)
China
China


PARAMETRIC INFO
Logic Family HC
Logic Function NAND
Number of Element Inputs 2-IN
Number of Element Outputs 1
Number of Elements per Chip 4
Number of Output Enables per Element 0
Number of Selection Inputs per Element 0
Output Type Push-Pull
Process Technology CMOS
Input Type Schmitt Trigger
Minimum Operating Supply Voltage (V) 2
Maximum Operating Supply Voltage (V) 6
Typical Operating Supply Voltage (V) 5
Maximum High Level Output Current (mA) -5.2
Maximum Low Level Output Current (mA) 5.2
Minimum Operating Temperature (°C) -40
Maximum Operating Temperature (°C) 85
Minimum Storage Temperature (°C) -65
Maximum Storage Temperature (°C) 150
Maximum Propagation Delay Time @ Maximum CL (ns) 120@2V|25@4.5V|21@6V
Absolute Propagation Delay Time (ns) 156
Propagation Delay Test Condition (pF) 50
Maximum Quiescent Current (uA) 2
 
PACKAGE INFO
Supplier Package SOIC
Basic Package Type Lead-Frame SMT
Pin Count 14
Lead Shape Gull-wing
PCB 14
Tab N/R
Pin Pitch (mm) 1.27
Package Length (mm) 8.75(Max)
Package Width (mm) 4(Max)
Package Height (mm) 1.5(Max)
Package Diameter (mm) N/R
Package Overall Length (mm) 8.75(Max)
Package Overall Width (mm) 6.2(Max)
Package Overall Height (mm) 1.75(Max)
Seated Plane Height (mm) 1.75(Max)
Mounting Surface Mount
Package Weight (g) N/A
Package Material Plastic
Package Description Small Outline IC
Package Family Name SO
Jedec MS-012AB
Package Outline Link to Datasheet
 
MANUFACTURING INFO
MSL 1
Maximum Reflow Temperature (°C) 260
Reflow Solder Time (Sec) 30
Number of Reflow Cycle 3
Standard J-STD-020D
Reflow Temp. Source Link to Datasheet
Maximum Wave Temperature (°C) N/R
Wave Solder Time (Sec) N/R
Lead Finish(Plating) Matte Sn|Au
Under Plating Material N/A|Pd over Ni
Terminal Base Material N/A|Cu Alloy
Number of Wave Cycles N/R
 
PACKAGING INFO
Packaging Suffix R
Packaging Tape and Reel
Quantity Of Packaging 2500
Reel Diameter (in) 13
Reel Width (mm) 16.4
Tape Pitch (mm) 8
Tape Width (mm) 16
Component Orientation Q1
Packaging Document Link to Datasheet
 
ECAD MODELS


FUNCTIONAL BLOCK DIAGRAM  


APPLICATIONS
• Alarm / tamper detect circuit
• S-R latch

Продукт RFQ