
|
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• Control inputs VIH/VIL levels are referenced to
VCCA voltage
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• VCC isolation feature – if either VCC input is at
GND, all are in the high-impedance state
|
• Fully configurable dual-rail design allows each port
to operate over the full 1.65-V to 5.5-V powersupply range
|
• Latch-up performance exceeds 100 mA per JESD
78, class II |
• ESD protection exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 100-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101) |
|
CATALOG |
SN74LVC8T245RHLR COUNTRY OF ORIGIN |
SN74LVC8T245RHLR PARAMETRIC INFO
|
SN74LVC8T245RHLR PACKAGE INFO
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SN74LVC8T245RHLR MANUFACTURING INFO
|
SN74LVC8T245RHLR PACKAGING INFO
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SN74LVC8T245RHLR ECAD MODELS
|
SN74LVC8T245RHLR APPLICATIONS
|
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COUNTRY OF ORIGIN |
Malaysia |
China |
|
PARAMETRIC INFO
|
Number of Channels |
8 |
Channel Type |
Bidirectional |
Logic Family |
LVC |
Process Technology |
CMOS |
Logic Function |
Voltage Level Translator |
Output Type |
3-State |
Minimum Operating Temperature (°C) |
-40 |
Maximum Operating Temperature (°C) |
85 |
Supplier Temperature Grade |
Commercial |
Minimum Operating Supply Voltage (V) |
1.65 |
Maximum Operating Supply Voltage (V) |
5.5 |
Typical Operating Supply Voltage (V) |
1.8|2.5|3.3|5 |
Maximum High Level Output Current (mA) |
-32 |
Maximum Low Level Output Current (mA) |
32 |
Maximum Quiescent Current (mA) |
0.015 |
Maximum Propagation Delay Time @ Maximum CL (ns) |
23.8@1.8V |
Absolute Propagation Delay Time (ns) |
32.2 |
|
|
PACKAGE INFO
|
Supplier Package |
VQFN EP |
Basic Package Type |
Non-Lead-Frame SMT |
Pin Count |
24 |
Lead Shape |
No Lead |
PCB |
24 |
Tab |
N/R |
Pin Pitch (mm) |
0.5 |
Package Length (mm) |
5.6(Max) |
Package Width (mm) |
3.6(Max) |
Package Height (mm) |
0.95(Max) |
Package Diameter (mm) |
N/R |
Package Overall Length (mm) |
5.6(Max) |
Package Overall Width (mm) |
3.6(Max) |
Package Overall Height (mm) |
1(Max) |
Seated Plane Height (mm) |
1(Max) |
Mounting |
Surface Mount |
Package Weight (g) |
N/A |
Package Material |
Plastic |
Package Description |
Very Thin Quad Flat No Lead Package, Exposed Pad |
Package Family Name |
QFN |
Jedec |
MO-241 |
|
|
MANUFACTURING INFO
|
MSL |
2 |
Maximum Reflow Temperature (°C) |
260 |
Reflow Solder Time (Sec) |
30 |
Number of Reflow Cycle |
3 |
Standard |
J-STD-020D |
Reflow Temp. Source |
Link to Datasheet |
Maximum Wave Temperature (°C) |
N/R |
Wave Solder Time (Sec) |
N/R |
Lead Finish(Plating) |
Au |
Under Plating Material |
Pd over Ni |
Terminal Base Material |
Cu Alloy |
Number of Wave Cycles |
N/R |
|
|
PACKAGING INFO
|
Packaging Suffix |
R |
Packaging |
Tape and Reel |
Quantity Of Packaging |
1000 |
Reel Diameter (in) |
7.09 |
Reel Width (mm) |
12.4 |
Tape Pitch (mm) |
8 |
Tape Width (mm) |
12 |
Component Orientation |
Q1 |
Packaging Document |
Link to Datasheet |
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ECAD MODELS
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APPLICATIONS
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• Personal electronic
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• Industrial
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• Enterprise
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• Telecom
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