|
|
• Advanced high-performance FPGA logic based on real 6-input lookup table (LUT) technology configurable as distributed memory. |
• 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data
buffering. |
• High-performance SelectIO™ technology with support for DDR3
interfaces up to 1,866 Mb/s. |
• High-speed serial connectivity with built-in multi-gigabit transceivers
from 600 Mb/s to max. rates of 6.6 Gb/s up to 28.05 Gb/s, offering a
special low-power mode, optimized for chip-to-chip interfaces. |
• A user configurable analog interface (XADC), incorporating dual
12-bit 1MSPS analog-to-digital converters with on-chip thermal and
supply sensors. |
• DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder
for high-performance filtering, including optimized symmetric
coefficient filtering. |
• Powerful clock management tiles (CMT), combining phase-locked
loop (PLL) and mixed-mode clock manager (MMCM) blocks for high
precision and low jitter. |
• Quickly deploy embedded processing with MicroBlaze™ processor. |
• Integrated block for PCI Express® (PCIe), for up to x8 Gen3
Endpoint and Root Port designs. |
• Wide variety of configuration options, including support for
commodity memories, 256-bit AES encryption with HMAC/SHA-256
authentication, and built-in SEU detection and correction. |
• Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flipchip packaging offering easy migration between family members in
the same package. All packages available in Pb-free and selected
packages in Pb option. |
• Designed for high performance and lowest power with 28 nm,
HKMG, HPL process, 1.0V core voltage process technology and
0.9V core voltage option for even lower power. |
|
CATALOG |
XC7A50T-L1CSG324I COUNTRY OF ORIGIN |
XC7A50T-L1CSG324I PARAMETRIC INFO |
XC7A50T-L1CSG324I PACKAGE INFO |
XC7A50T-L1CSG324I PACKAGING INFO |
|
COUNTRY OF ORIGIN |
Philippines |
Taiwan (Province of China) |
|
PARAMETRIC INFO |
Device Logic Units |
52160 |
Device Logic Cells |
52160 |
Maximum Number of User I/Os |
210 |
Number of I/O Banks |
5 |
Device Number of DLLs/PLLs |
5 |
Number of Multipliers |
120 (25x18) |
Number of Regional Clocks |
4 |
Maximum LVDS Data Rate (Mbps) |
1250 |
Tradename |
Artix |
RAM Bits (Kbit) |
2700 |
Total Number of Block RAM |
75 |
Program Memory Type |
SRAM |
Maximum Distributed RAM Bits |
614400 |
Family Name |
Artix-7 |
Process Technology |
28nm |
Speed Grade |
3 |
Transceiver Blocks |
16 |
Transceiver Speed (Gbps) |
6.6 |
Dedicated DSP |
120 |
JTAG Support (-) |
Yes |
PCI Blocks |
1 |
Copy Protection |
Yes |
Shift Registers |
Utilize LUT |
Programmability |
Yes |
In-System Programmability |
Yes |
Reprogrammability Support |
Yes |
Number of Global Clocks |
32 |
Maximum Operating Supply Voltage (V) |
1.05 |
I/O Voltage (V) |
1.2|1.35|1.5|1.8|2.5|3.3 |
Minimum Operating Temperature (°C) |
-40 |
Maximum Operating Temperature (°C) |
100 |
Temperature Flag |
Jun |
Supplier Temperature Grade |
Industrial |
Digital Control Impedance |
No |
Minimum Operating Supply Voltage (V) |
0.95 |
Typical Operating Supply Voltage (V) |
1 |
Maximum Storage Temperature (°C) |
150 |
Minimum Storage Temperature (°C) |
-65 |
|
|
PACKAGE INFO |
Supplier Package |
CSBGA |
Basic Package Type |
Ball Grid Array |
Pin Count |
324 |
Lead Shape |
Ball |
PCB |
324 |
Tab |
N/R |
Pin Pitch (mm) |
0.8 |
Package Length (mm) |
15 |
Package Width (mm) |
15 |
Package Height (mm) |
0.9 |
Package Diameter (mm) |
N/R |
Package Overall Length (mm) |
15 |
Package Overall Width (mm) |
15 |
Package Overall Height (mm) |
1.5(Max) |
Seated Plane Height (mm) |
1.5(Max) |
Mounting |
Surface Mount |
Package Weight (g) |
N/A |
Package Material |
Plastic |
Package Description |
Chip Scale Ball Grid Array |
Package Family Name |
BGA |
Jedec |
MO-275KKAB-1 |
Package Outline |
Link to Datasheet |
|
|
PACKAGING INFO |
Packaging |
Tray |
Packaging Document |
Link to Datasheet |
|
|