Cadence Introduces Complete DRAM Verification Solutions for Automotive, Data Center and Mobile Applications
Jan 21,2022
Cadence Electronics (Cadence Corporation, NASDAQ: CDNS) today announced an innovative DRAM verification solution that enables customers to test and optimize system-on-chip (SoC) designs for data center, consumer, mobile and automotive applications. This complete DRAM verification solution increases verification throughput by 10X, allowing customers to quickly and efficiently perform IP-to-SoC-level verification of advanced designs with multiple DDR interfaces.
Current SoC designs utilize advanced memory technologies such as LPDDR5x, DDR5, HBM3, and GDDR6, which require rigorous verification at the PHY and IP level to ensure compliance with JEDEC standards and verification at the SoC level to meet application-specific system performance Definition and data and cache coherency requirements.
"DRAM memory verification requires a unique approach to ensuring that all timing, power, and throughput requirements are met under a variety of conditions," said Paul Cunningham, senior vice president and general manager of the Systems and Verification R&D Group at Cadence. The first complete DRAM verification solution, customers can efficiently verify IP designs and ensure their designs meet JEDEC standard specifications and application-specific performance metrics for memory subsystems, providing the fastest path to IP and system verification closure."
New DRAM verification solution enables IP-level verification with Cadence® PHY VIP and memory models, and direct and seamless SoC-level verification with Cadence System VIP solutions including System Performance Analyzer, System Traffic Libraries and System Scoreboard, all with built-in integration and content for DRAM interfaces, for fast and efficient verification of memory subsystems and SoCs for emulation and hardware-accelerated environments.
The solution also includes Cadence TripleCheck™ technology, which provides users with a specification-linked verification plan, including JEDEC, DFI and PHY comprehensive coverage models and test components to ensure compliance with interface specifications.
“Micron is committed to leading the development of next-generation memory technologies that drive value from the data center to the intelligent edge, and across the client and mobile user experience,” said Malcolm Humphrey, vice president and general manager of the Compute DRAM Products Group at Micron. The Cadence collaboration accelerates the development of an ecosystem that can deliver innovative memory solutions."
The new verification solution for DRAM verification is part of a broader Cadence verification flow that includes Palladium® Z2 hardware emulation, Protium™ X2 prototyping, Xcelium™ software emulation, Jasper® Formal Verification Platform, Helium™ Virtual and Hybrid Studio and vManager™ Verification Management Platform Verification Management Platform. Cadence's full verification flow provides the highest verification throughput at an extremely cost-effective price. The DRAM verification solution and verification flow support the company's Intelligent System Design™ strategy for SoC design excellence.
Current SoC designs utilize advanced memory technologies such as LPDDR5x, DDR5, HBM3, and GDDR6, which require rigorous verification at the PHY and IP level to ensure compliance with JEDEC standards and verification at the SoC level to meet application-specific system performance Definition and data and cache coherency requirements.
"DRAM memory verification requires a unique approach to ensuring that all timing, power, and throughput requirements are met under a variety of conditions," said Paul Cunningham, senior vice president and general manager of the Systems and Verification R&D Group at Cadence. The first complete DRAM verification solution, customers can efficiently verify IP designs and ensure their designs meet JEDEC standard specifications and application-specific performance metrics for memory subsystems, providing the fastest path to IP and system verification closure."
New DRAM verification solution enables IP-level verification with Cadence® PHY VIP and memory models, and direct and seamless SoC-level verification with Cadence System VIP solutions including System Performance Analyzer, System Traffic Libraries and System Scoreboard, all with built-in integration and content for DRAM interfaces, for fast and efficient verification of memory subsystems and SoCs for emulation and hardware-accelerated environments.
The solution also includes Cadence TripleCheck™ technology, which provides users with a specification-linked verification plan, including JEDEC, DFI and PHY comprehensive coverage models and test components to ensure compliance with interface specifications.
“Micron is committed to leading the development of next-generation memory technologies that drive value from the data center to the intelligent edge, and across the client and mobile user experience,” said Malcolm Humphrey, vice president and general manager of the Compute DRAM Products Group at Micron. The Cadence collaboration accelerates the development of an ecosystem that can deliver innovative memory solutions."
The new verification solution for DRAM verification is part of a broader Cadence verification flow that includes Palladium® Z2 hardware emulation, Protium™ X2 prototyping, Xcelium™ software emulation, Jasper® Formal Verification Platform, Helium™ Virtual and Hybrid Studio and vManager™ Verification Management Platform Verification Management Platform. Cadence's full verification flow provides the highest verification throughput at an extremely cost-effective price. The DRAM verification solution and verification flow support the company's Intelligent System Design™ strategy for SoC design excellence.